SPTS Technologies, a leading manufacturer of etch, deposition and thermal processing equipment for the semiconductor industry, today announced that it has signed an agreement with CEA-Leti in Grenoble, France, to develop 3D-TSV technologies The two-year agreement enters under the framework of the Nanoelec Research Technology Institute program which is led by CEA-Leti, and covers co-development of a range of deposition processes for next-generation 3D high aspect ratio through-silicon-via (TSV) solutions. The agreement builds on the long established relationship between the partners who have already collaborated in the past, particularly on the development and optimization of an advanced MOCVD TiN barrier for high aspect ratio TSV.
3D packaging of semiconductor devices, using TSVs to connect stacked die, is accepted as a critical technology to deliver industry performance goals without exceeding power budgets. To scale future 3D devices, new techniques will be needed to manufacture TSV’s of smaller diameter and higher aspect ratio than are used today. Under this agreement, SPTS and CEA-Leti aim to develop production worthy solutions to address these challenges. Previous collaboration has resulted in a number of key advancements in the formation of TSVs using SPTS’ deep reactive ion etch (DRIE), chemical vapor deposition (CVD) and physical vapor deposition (PVD). One of the key achievements includes optimization of an advanced metal organic chemical vapor deposition (MOCVD) TiN barrier for high aspect ratio TSV.
“The results previously achieved keeps SPTS at the forefront of 3D-TSV development,” said Kevin Crofton, president and chief operating officer of SPTS. “In partnership with CEA-Leti, we plan now to develop technology and processes that will further extend TSV aspect ratios beyond 20:1, with a particular focus on developing an MOCVD copper process as a seed layer to replace ionized PVD.”
“The work with SPTS and other partners will create solutions that will be transferred into industry,” said Dr. Laurent Malier, CEO of CEA-Leti and President of the Nanoelec RTI board. “Combining Leti’s integration expertise with the specific process knowledge of successful equipment manufacturers like SPTS enables innovation and allows us to create an optimised, cost-effective process flow for volume manufacturing of 3D-IC devices.”